1. Field of the Invention
The present invention generally relates to Content Addressable Memories (CAMs), and particularly relates to reducing CAM power consumption without adversely impacting CAM performance.
2. Relevant Background
Unlike Random Access Memory (RAM) in which the RAM returns a data word stored at an address supplied to the RAM, a Content Addressable Memory (CAM) searches its entire memory for a data pattern that matches a search word input to the CAM. If the data pattern is found, the CAM returns a list of one or more storage addresses where the word was found. In some CAMs, the data word or other associated data is also returned. Thus, CAMs are often used an associative array.
CAMs comprise a plurality of entries, each entry having a number of CAM cells configured to store data. The CAM cells may be binary (store binary data) or ternary (store binary data or a ‘don't care’ state). Each CAM cell is coupled to a match line. During a CAM search operation, a search field is provided to the CAM. In response to the search field input, each match line indicates whether its respective CAM cell contains data matching some portion of the search field. After the search operation completes, match lines are conventionally restored to a pre-evaluation state to improve CAM performance during a subsequent search. For example, match lines are conventionally pre-charged high to a logic one value during a pre-evaluation period.
During a subsequent CAM search operation, match lines associated with CAM cells that do not contain matching data are discharged. Only those match lines coupled to CAM cells that store matching data remain charged high. As such, only one CAM cell associated with an entry need contain mismatching data for the entry to be identified as containing a mismatched data pattern. This is referred to as a miss. Conversely, if each cell in an entry yields a match, the entry is identified as containing a matching pattern, which is referred to as a hit.
Some conventional CAMs contain multiple levels of hierarchical match lines for reducing capacitive loading on the match lines, which affects CAM performance and power consumption. In such multi-level hierarchical CAMs, local match lines serving a group of CAM cells are coupled to a single global match line. A mismatch indicated by one or more local match lines is reflected by the corresponding global match line. As such, a global match line indicates a miss if any one of its corresponding local match lines indicates a miss. Conversely, the global match line indicates a hit if all of its corresponding local match lines indicate a hit. Depending on CAM size, one or more intermediary levels of match lines may be included between local match lines and a corresponding global match line to further reduce capacitive loading.
Regardless of the particular CAM architecture, some applications that process CAM search results may only need the search results for a subset of the CAM entries. For example, some applications may discard or ignore hit/miss search results for certain portions of particular CAM entries while using the search results associated with other portions of the entries. One conventional approach for ignoring hit/miss search results for particular CAM cells is to disconnect CAM cells not of interest from their respective match lines. For example, a transistor device may be placed in series between the output node of a CAM cell and its respective match line. When the transistor is switched off, the CAM cell is decoupled from its match line. As such, the content of the CAM cell does not affect the state of the CAM cell's match line. That is, the match line remains in its pre-evaluation state, e.g., pre-charged high state regardless of whether its corresponding CAM cell contains matching data or not. However, power is consumed pre-charging the CAM cell's match line during the pre-evaluation period even though the search results associated with that CAM cell will be ignored. In addition, when the gating transistor is switched on, the transistor couples the output node of the CAM cell to the match line. Such a configuration adds additional capacitance to the output node of CAM cells, thus slowing match line operations and consuming additional power.
Another conventional approach for ignoring particular search results in multi-level hierarchical CAMs is to disable the global match line enable circuitry associated with local match lines not of interest. For example, the clock signal that controls whether a pre-charged global match line may be discharged is gated by an enable signal. If the clock signal is disabled, the global match line remains in its pre-charged state regardless of the state of the local match lines coupled to it. As a result, only global match lines that are enabled during a CAM evaluation period are affected by the state of their corresponding local match lines. Power is still consumed pre-charging the corresponding global and local match lines when the global match line enable circuitry is disabled.